1. Field of the Invention
The present invention relates to a self-refresh circuit and operation within a semiconductor memory device. More particularly, the invention relates to a self-refresh control circuit, a semiconductor memory device including a self-refresh control circuit, and a method of controlling a refresh operation in a semiconductor memory device.
2. Description of the Related Art
Random access memory (RAM) is widely used to store data and/or related commands within a system or host device. RAM has several advantages over other forms of memory including an ability to access all addresses in the RAM at substantially the same speed.
RAM may be further classified as static RAM (SRAM) and a dynamic RAM (DRAM). SRAM preserves stored data so long as the SRAM is powered. This data preservation capability within SRAM is enabled by a relatively complicated configuration of four or six transistors arranged in a symmetric latch structure. As a result, SRAM is relatively costly to manufacture and difficult to integrate. In contrast, DRAM may be implemented with a single access transistor and a corresponding storage node such as a capacitor. Accordingly, DRAM is cheaply manufactured and relatively easy to integrate. Unfortunately, DRAM gradually loses stored data because the storage node commonly suffers from current leakage. This DRAM characteristic conventionally mandates the inclusion of a refresh circuit adapted to periodically restore lost charge indicative of stored data to the storage node. The periodicity of the refresh operation is referred as “a refresh rate.”
Different operating modes for the system or host device incorporating DRAM will often dictate the refresh rate and other related parameters for the refresh operation. During a standby mode or similar powered-down mode of operation for a system or host device, the data stored in DRAM is often preserved by application of a so-called “self-refresh operation”. Thus, by means of an effective self-refresh operation, DRAM may be implemented to mimic the performance advantages of SRAM, albeit generally at lower cost.
FIG. 1 is a block diagram illustrating a conventional semiconductor memory device. The exemplary semiconductor memory device illustrated in part by FIG. 1 is further disclosed in U.S. Pat. No. 5,610,863, the subject matter of which is hereby incorporated by reference.
Referring to FIG. 1, a semiconductor memory device 10 includes a memory cell array 20, a voltage generator 30 and a row selection circuit 40. Other conventionally understood components such as the sense amplifier are omitted from FIG. 1 for the sake of clarity.
As is conventional, memory cell array 20 includes a plurality of memory cells coupled to word lines and bit lines. The memory cells are typically divided into designated block units and/or bank units. For convenience of illustration, only a single memory cell is illustrated in memory cell array 20 of FIG. 1. This DRAM memory cell is coupled to a word line WLi and a bit line BLj, and includes a storage capacitor CS and access transistor TA.
Voltage generator 30, which may be referred to as a boosting circuit, generates a high voltage by boosting a power supply voltage using internal pumping capacitors. The generated high voltage is provided to circuitry associated with memory cell array 20.
Row selection circuit 40 includes a row decoder 41 and a word line driving circuit 42. Row decoder 41 decodes a row address signal RADD and provides a decoded row address signal DRADD driving a selected word line (i.e., WLj). Word line driving circuit 42 includes a plurality of drivers respectively coupled to word lines. Only one driver is illustrated in FIG. 1 for convenience of illustration. Each driver circuit 42 including a pair of transistors PM and NM applies a high level voltage to the selected word line and a low level voltage to unselected word lines as dictated by the decoded row address signal DRADDi of the decoded row address signal. The timing of the decoded row address signal DRADDi to the selected word line by driving circuit 42 is controlled by a word line enable signal WEN. For example, the decoded row address signal DRADDi may be applied to the selected word line by driving circuit 42 when word line enable signal WEN is activated (i.e., is logically “high”).
In general, a voltage higher than the power supply voltage is applied to the selected word line in order to turn ON the access transistor TA. Voltage generator 30 generates such this high voltage in response to the word line enable signal WEN and provides the high voltage to internal circuits such as word line driving circuit 42.
FIG. 2 is a related timing diagram illustrating the self-refresh operation of the conventional semiconductor memory device shown in FIG. 1.
Referring to FIGS. 1 and 2, when a self-refresh signal SREF is activated to indicate operation in a self-refresh mode, voltage generator 20 generates a pumping signal VCTR to control the level of an output voltage VOUT in response to the word line enable signal WEN that is also activated during a refresh period tREF. Voltage generator 30 periodically boosts the output voltage VOUT in response to the pumping signal VCTR and the output voltage VOUT is provided to the word line driving circuit 42.
It takes a predetermined period of time to charge the pumping capacitor(s) used to implement voltage generator 30. Accordingly the output voltage may not be sufficiently boosted during an initial stage of the boosting operation, if the boosting operation is performed in synchronization with the word line enable signal WEN. Thus, if the selected word line is enabled while the output voltage VOUT is insufficiently charged, the stored data may be altered by application of an abnormal refresh operation. To prevent the abnormal refresh operation, the word line enable signal WEN should be activated in the refresh mode longer than in a read mode. Nevertheless, the word line may be developed while the output voltage VOUT has an insufficient level, thereby causing the abnormal refresh operation.
FIG. 3 is another timing diagram illustrating a self-refresh operation in another conventional semiconductor memory device.
Referring to FIG. 3, a voltage generator maintains the output voltage VOUT at a high voltage level VPP. In such cases, the timing of the word line enable operation may not be properly correlated with the timing of the pumping operation for the output voltage VOUT. Thus, the refresh period may be reduced. Power consumption, however, is significantly increased due to the consistent pumping operation of the voltage generator.
Accordingly, conventional self-refresh operations experience problems associated with abnormal refresh operation and/or the excessive power consumption.